IN12 · A stable trace can be an alias

Digital Oscilloscope

When can a stable waveform be an illusion created by sampling? A stable trace can still be an alias. Different signals can pass through the same sampled values, and a trigger can align those values repeatedly. Check the sampling rate and analog bandwidth, then measure the stored samples; a smooth connecting line cannot restore changes that were never recorded.

Capture pulses and two-tone signals through a probe, analog bandwidth and ADC. Compare raw samples with their linear display and measure the same record.

A stable trace starts with a clock

Apparent sampled period $1.00\,\mathrm{ms}$

Sample edge, ten–ninety percent $17.8\,\mathrm{\mu s}$

Sample absolute peak $1.00\,\mathrm V$

Samples in shown record $800$

Generator signalSampling clockGenerator frequency

f/\mathrm{Hz}

1000

Requested record window

T/\mathrm{ms}

4

Analog bandwidth

B/\mathrm{Hz}

20000

Digital trigger level

V_T/\mathrm V

0

Drag the pink trigger knob or move the physical probe between signal and return.

A calibrated triggered record is ready.

Trigger, converter, calibration and model

Trigger modeTrigger slopeProbe contactADC full voltage spanADC bitsPretrigger fraction

0.25

Generator half-amplitude in volts

1

Generator offset in volts

0

Pulse duty fraction

0.4

Second frequency / first

2

Second-tone amplitude fraction

0.3

Actual ADC gain factor

1.012

Actual ADC offset in volts

0.006

Clock deviation in parts per million

20

Aperture jitter bound in nanoseconds

0

Input noise bound in volts

0.0003

Source resistance in ohms

50

Acquisition seed

185

The unity buffer has a one-megaohm input; source resistance loads that input. A single-pole analog filter precedes the ADC. Probe capacitance, cable delay and reflections are omitted.

The clock gate calibrates mean timing, not individual aperture jitter. Triggering reads ADC codes; auto waits three requested record lengths. Linear interpolation only joins acquired samples. Hardware motion replays the capture at a schematic speed.

Memory accepts 32–4096 samples. A normal-mode trigger failure retains the preceding capture. Changed ADC or clock hardware needs a fresh calibration; stored exports retain their original standards.

Model assumptions

A simulated real-time, single-channel DC-coupled instrument uses a unity-gain buffered probe with a one-megaohm input, resistive source loading and a settled single-pole analog front end. Probe capacitance, cable delay, reflections and nonlinear electronics are omitted. A signed round-to-nearest ADC includes declared gain, offset, bounded noise and optional aperture jitter. Digital edge triggering uses acquired codes with a two-code rearm band; normal mode retains the preceding record on failure, while auto mode captures after a three-record-length timeout. Calibration reads known DC levels and a one-second clock gate. Automatic measurements use acquired codes and their saved calibration. Source and filtered curves are separate simulation references; no equivalent-time acquisition or commercial scope is reproduced.

What did the sampling clock actually keep?

Saved simulated record · raw ADC acquisition

t/\mathrm{ms}

V/\mathrm V

ADC points and linear displayProbe input · model referenceFiltered input · model reference

Gold and violet are separate simulation references; turquoise is acquired data. Drag the pink marker to preview a new digital trigger; keeping a capture freezes its samples and standards.

Reopen a kept record

Raw codes, clock and calibration provenance

First and last samples of the shown acquisition
Sample	ADC code	$t/\mathrm{ms}$	$V/\mathrm V$	Overload

Exports retain every code, nominal timestamp, overload mask, trigger index/fraction, range, known-reference observations, version and seed. Realized jitter times are simulation provenance, not measured timestamps.

Start with the essentials

Focus question: How can a stable slow wave come from a much faster input?
One-sentence intuition: Trigger alignment stabilizes a record; sampling and analog bandwidth determine what information reached it.

Core mathematical model

A declared single-pole analog input

H(f)=\frac{1}{1+\mathrm i f/B},\qquad t_{10\text{–}90}=\frac{\ln9}{2\pi B}

The rise-time relation is exact for a settled ideal step through this chosen one-pole filter. A finite pulse and sample-derived levels can give a different measured edge time.

Voltage and time come from saved standards

V_n=V_{\rm ref}\frac{c_n-\bar c_0}{\bar c_{\rm ref}-\bar c_0},\qquad \Delta t=\frac{T_g f_{\rm cal}}{N_g f_s}

Known DC levels set volts per code. A one-second reference gate and its observed tick count calibrate the common clock. Aperture jitter is not measured by that gate.

Two frequencies can have the same samples

\sin\!\left(2\pi\frac{1100n}{1000}\right)=\sin\!\left(2\pi\frac{100n}{1000}\right)

This equality describes ideal instantaneous samples before filtering. The full instrument also changes amplitude and phase in its analog front end.

Common difficulties

A smooth line is not extra data

Typical misconceptionIf the connecting line looks smooth, the missing fast motion has been recovered.

Better mental modelLinear interpolation passes through the stored samples and adds no independent observations between them.

Peak values can be clipped

Typical misconceptionThe largest displayed sample always gives the input peak.

Better mental modelAn overload mask marks samples outside ADC code range. A clipped peak is only a lower bound; clipped edge times are withheld.

Run the experiment

01
Compare an edge with its samples
Choose An edge stands still, then use Edge zoom below the apparatus.
What to observe: The teal dots and linear display share one acquired record. Its measured rise comes from the stored 10 and 90 percent crossings.
02
Change the sampling clock
Choose Fast becomes slow and compare the gold input reference with the turquoise record.
What to observe: The input is faster than the clock can distinguish. Its stable apparent period describes the sampled trace.
03
Miss the trigger condition
Raise the trigger level above the signal, then compare normal and auto trigger mode in the advanced controls.
What to observe: Normal mode retains the prior capture. Auto mode keeps actual samples after its timeout, marked as untriggered.

Digital Oscilloscope

What did the sampling clock actually keep?

Read the samples before trusting the line

Core mathematical model

A declared single-pole analog input

Voltage and time come from saved standards

Two frequencies can have the same samples

Common difficulties

A smooth line is not extra data

Peak values can be clipped

Run the experiment

Compare an edge with its samples

Change the sampling clock

Miss the trigger condition

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